The present invention relates to a data processor, and more particularly, to an error correction processor for adding an error detection code and an error correction code to digital data when recording the digital data, which is in a predetermined format and output from a host computer, on a recording medium, such as a CD-Recordable (CD-R) or CD-Rewritable (CD-RW) disc.
An optical disc recorder, which functions as a data recorder, is known in the prior art to record data on an optical disc, which is a recording medium. An example of such an optical disc recorder is a CD-R/RW drive that uses a CD-R disc, to which data may be written only once, or a CD-RW disc, to which data may be written repetitively. In a CD-R/RW system, an error detection code (EDC) and an error correction code (ECC) are added to the recording data to correct code errors when reproducing the data on the disc.
Referring to FIG. 1, a prior art CD-R/RW system 100 includes a CD-ROM decoder 1, a digital signal processor 2, an analog signal processor 3, a pickup 4, a pickup controller 6, a buffer RAM 7, and a control microcomputer 8.
The CD-ROM decoder 1 receives 2048 bytes of data from a host computer 120 and adds an error correction code (ECC) and an error detection code (EDC) to the data to generate CD-ROM data. The CD-ROM data includes multiple blocks. As shown in FIG. 2, each block is configured from 2,352 bytes (24 bytes×98 frames). In mode 1, each block includes synchronization data (12 bytes), a header (4 bytes), user data (2,048 bytes), the EDC (4 bytes), a space (8 bytes), and the ECC (276 bytes). In each block, the data excluding the synchronization data (12 bytes), that is, 2,340 bytes of data, undergoes scramble processing. In the CD-ROM decoder 1, an encoding (recording) device is incorporated in a decoding (reproduction) device, which performs an error correction process and error detection process on the CD-ROM data that is read from an optical disc. Further, in the CD-ROM decoder 1, the reproducing system and the recording system are normally combined. The recording system of the CD-R/RW system 100 is described here, but description of the reproducing system is omitted.
The digital signal processor 2 receives the CD-ROM data from the CD-ROM decoder 1 in single frame units (24 bytes), performs a predetermined operation on the CD-ROM data to generate codes C1 and C2 based on a Cross-Interleave Reed-Solomon Code (CJRC), and adds codes C1 and C2 to the CD-ROM data. The digital signal processor 2 interleaves and performs eight to fourteen modulation (EFM) on the CD-ROM data, to which the codes C1 and C2 are added, to generate an analog signal. The analog signal processor 3 receives the analog data from the digital signal processor 2 in a serial manner. Then, the analog signal processor 3 reads changes in the level of the analog data to control the emission of a laser beam from the pickup 4 toward the optical disc 5.
In addition to emitting a laser beam toward the optical disc 5 to read data from the optical disc 5, the pickup 4 records the data encoded by the CD-ROM decoder 1 on the optical disc 5. The optical disc 5 may be, for example, a CD-R disc having a recording layer to which the writing of data is enabled only once or a CD-RW disc having a recording layer to which data may be rewritten a number of times. In the CD-R disc, data is recorded by melting the recording layer, which is formed from organic pigments, with the heat of a high power laser beam and forming pits. In the CD-RW disc, sudden heating with a laser beam and sudden cooling are performed so that an amorphous phase is formed in the recording layer to change the reflectance of light and record data. The pickup controller 6 controls the position of the pickup 4 relative to the optical disc 5 based on the signal read from the optical disc 5.
The buffer RAM 7, which is connected to the CD-ROM decoder 1, temporarily stores the CD-ROM data provided to the CD-ROM decoder 1 from the host computer 120. In the CD-ROM decoder 1, the EDC and ECC are obtained for each block. Further, the obtained EDC and ECC are added to the data of the block. Thus, the CD-ROM decoder 1 requires at least a single block of the CD-ROM data. Accordingly, the buffer RAM 7 stores a single block of the CD-ROM data that is required for the CD-ROM decoder 1 to perform processing.
The control microcomputer 8, which is a one-chip microcomputer having a memory that stores a control program, controls the operation of the CD-ROM decoder 1 in accordance with its control program. Further, the control microcomputer 8 stores command data, which is provided from the host computer 120, in its memory and controls the CD-ROM decoder 1, the digital signal processor 2, the analog signal processor 3, and the pickup controller 6 in accordance with the command from the host computer 120.
While receiving the CD-ROM data from the host computer 120 and providing the CD-ROM data to the digital signal processor 2, the CD-ROM decoder 1 adds the EDC and the ECC to the CD-ROM data. The CD-ROM decoder 1 includes an plurality of circuits including an error correction circuit and an error detection circuit. The processes performed by the error correction and error detection circuits are performed in a sequential manner. Thus, in accordance with each process, the buffer RAM 7 is accessed in a time-divisional manner. In this case, when, for example, error correction is performed, the error correction circuit occupies the access to the buffer RAM 7. However, other processing circuits are also permitted access to the buffer RAM 7 in this state. Accordingly, regardless of how fast error correction or error detection are performed, a certain length of time is required to complete processing in the entire CD-ROM decoder 1. Thus, it is difficult to further increase the processing speed of the CD-ROM decoder 1.